Design of high speed and low power 5:3 compressor architectures using novel two transistor XOR gates

The paper proposes architectures of 5:3 compressor designs for low power multiplication purposes. The architecture explores the essence of two transistor multiplexer design and novel two transistor XOR gates for the proposed topology with least number of transistors for logic level implementation. The modified and proposed compressor designs reduce the stage delays, transistor count, PDP (power delay product), EDP (energy delay product) and area by utilizing the combinations of XORXNOR gates, MUX circuits and transistor level implementation contrasted with the conventional designs. Simulation studies have been carried out in 65nm, 90nm, 130nm technologies in Cadence Spectre. Index Terms Compressor, Low Power, Layout, Multiplexer, Multiplier, XOR-XNOR